Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwave ovens to personal computers. Designing and fabricating microcircuit devices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit being designed, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” will verify a design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected.
Several steps are common to most design flows for digital mircocircuit devices. Initially, the specification for the new microcircuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logical of the circuit is then analyzed, to confirm that the logic incorporated into the design will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This logical generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the functions desired for the circuit. This analysis is sometimes referred to as “formal verification.”
Once the relationships between circuit devices have been established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements define the shapes that will be created in various materials to actually manufacture the circuit device components (e.g., contacts, gates, etc.) making up the circuit. While the geometric elements are typically polygons, other shapes, such as circular and elliptical shapes, also may be employed. These geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Geometric elements also are added to form the connection lines that will interconnect these circuit devices.
With a layout design, each physical layer of the microcircuit will have a corresponding layer representation, and the geometric elements described in a layer representation will define the relative locations of the circuit device components that will make up a circuit device. Thus, the geometric elements in the representation of an implant layer will define the regions where doped material will be located, while the geometric elements in the representation of a metal layer will define the locations where conductive wires will be formed to connect the circuit devices. Typically, a designer will perform a number of analyses on the layout design. For example, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships described in the device design. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, it may be modified to include the use of redundant or other compensatory geometric elements intended to counteract limitations in the manufacturing process, etc.
After the layout design has been finalized, then it is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process. Examples of such formats are MEBES, for raster scanning machines manufactured by ETEC, an Applied Materials Company, the “.MIC” format from Micronics AB in Sweden, and various vector scan formats for Nuflare, JEOL, and Hitachi machines, such as VSB12 or VSB12. The written masks or reticles can then be used in a photolithographic process to expose selected areas of a wafer in order to produce the desired integrated circuit devices on the wafer.
One issue in particular that occurs with both digital and analog integrated circuits is electromigration. Electromigration is the gradual displacement of material caused by the movement of the ions which make up the lattice of a conductive material. The cause of electromigration is generally considered to be the momentum transfer from electrons traveling through the conductive material to ions that make up the lattice. A microcircuit device typically includes a dense array of narrow, thin-film metallic conductors that serve to transport current between various circuit elements of the microcircuit device. These metallic conductors are sometimes referred to as interconnects. Due to continuing miniaturization of microcircuit devices, interconnects are subject to increasingly high current densities. Under such conditions, electromigration can cause interconnects to fail electrically in short times and reduce the circuit lifetime to an unacceptable level. It is thus important to identify interconnects in a design that are susceptible to electromigration effects.
Conventional detection of interconnects at risk from electromigration uses techniques akin to finite element analysis, but these techniques are extremely resource intensive and are impractical for full-chip analysis. Alternate approaches determine the expected current density for an interconnect in a design (e.g., the current density that will be expected in the corresponding physical interconnect manufactured from the design). These techniques, however, typically determine whether the expected current density will cause the physical interconnect to fail quickly with use. They do not determine whether or not the physical interconnect will degrade over longer periods of time due to electromigration, or at what rate the degradation will occur.